Ребята из FPGA комунити каждый день делают небольшую подборку новостей из мира FPGA и решили поделиться ею с читателями хаба FPGA. Внимание: возможны повторы!
Свежие отечественные статьи
Основы статического временного анализа. Часть 2.2: System Synchronous Output Delay Constraint.
Подключаем Slave-устройства с шиной Wishbone к системе на базе LiteX
Остальное англоязычное
PYNQ Now Available for the Kria KV260 Vision AI Starter Kit - Announcements - PYNQ
Introduction to FPGA Part 11 - RISC-V Softcore Processor | Digi-Key Electronics - YouTube
Measuring Circuit Delay for FPGA Timing using the ADP3450 - Hackster.io
AXI4-Lite Interface Wrapper for Custom RTL in Vivado 2021.2 - Hackster.io
Hello 2022 with Vintage Bubble Displays on the Arty Z7 - Hackster.io
Blueshift Memory adds UK industry veterans to advisory board
FPGA Vs Microcontrollers - Another Approach to Embedded Design
Formal verification for SystemC/C++ designs - Tech Design Forum Techniques
FPGA Video AI deployment – From platform creation to AI deployment - Part 1
Prototype and Adjust a Deep Learning Network on FPGA Video - MATLAB & Simulink
Intel’s FPGA Day Unveils 3 Collabs to Create More FPGA-based IPU Designs - News
JLPEA | Free Full-Text | CORDIC Hardware Acceleration Using DMA-Based ISA Extension
Microcontroller in FPGA? This is how to do it ... | Step by Step Tutorial | Adam Taylor - YouTube
QuickLogic Announces Australis™ eFPGA IP Generator :: QuickLogic Corporation (QUIK)
Increase your productivity with Continuous Integration flows
How a robust FPGA supply chain assures defense industry preparedness - Military Embedded Systems
New RF FPGA solutions transform EW platforms - Military Embedded Systems
FPGA Frontrunners Meet & Greet Tickets, Wed 23 Mar 2022 at 09:30 | Eventbrite
3U VPX FPGA modules first to market with high-bandwidth memory
Build your own video pipeline with PYNQ composable overlays | LinkedIn
RTLvision PRO Datasheet: Understand, Debug, and Integrate RTL Code, Easily - EDA Direct
CPU, GPU, FPGA or TPU: Which one to choose for my Machine Learning training? – InAccel
The Future of Embedded FPGAs — eFPGA: The Proof is in the Tape Out - Circuit Cellar
RehanEjaz/Pwm-FPGA-motor-speed-ctrl: Speed controller for DC motor to implement on FPGA
Are We Poised to Turn the Optical Computing Corner? – EEJournal
How does a flip flop work and why does it have setup & hold time? - YouTube
Netnod goes live with Arista FPGA implementation of Network Time Security (NTS) | Netnod
China Approves Chipmaker AMD’s $35 Billion Acquisition of Xilinx - Bloomberg
GOWIN Semiconductor USB 2.0 PHY Interface and Device Controller IPs Achieve USB-IF Certification
The Future of Embedded FPGAs — eFPGA: The Proof is in the Tape Out - Circuit Cellar
Mastering the Migration Journey from Spartan-6 FPGAs to 7 Series and Beyond
Infineon Accelerates Development of IBIS-AMI Models for SerDes Designs - MATLAB & Simulink
How does a flip flop work and why does it have setup & hold time? - YouTube
China Approves Chipmaker AMD’s $35 Billion Acquisition of Xilinx - Bloomberg
Accelerate AI applications using VITIS AI on Xilinx ZynqMP UltraScale+ FPGA - Softnautics
Ethernet Communication using TCP protocol in Zynq processor in VIVADO 2018.2. - YouTube
Deploying Deep Learning on Embedded CPUs, GPUs, and FPGAs Video - MATLAB
FPGA programming - what is it, how it works and where it can be used - CodiLime
Taming the Accelerator Cambrian Explosion with Omnia | LinkedIn
Deep physical neural networks trained with backpropagation | Nature
The Future of Embedded FPGAs — eFPGA: The Proof is in the Tape Out - Circuit Cellar
3U VPX FPGA modules first to market with high-bandwidth memory
Analysis of the sales market for FPGA modules up to 2029 - winnquick.com
Video: APA7-500 Series: User Configurable FPGA I/O Modules | Acromag
DO-254 Training: Learn This Important Standard for Aviation Hardware Safety | LinkedIn
Will the rise of AI and the Internet of Things subvert the design of Embedded Systems? | LinkedIn
Lattice Certus-NX Versa Evaluation Board Roadtest Review - element14 Community
Accelerate AI applications using VITIS AI on Xilinx ZynqMP UltraScale+ FPGA - Softnautics