Провели мероприятие в Калифорнийском политехническом государственном университете в Сан-Луис-Обиспо. Докладчиками были: ваш покорный слуга Юрий Панчул, два американских инженера проектирующие чип по ускорению ИИ, и китайский студент из Университета Калифорнии в Санта-Барбаре. Идея мероприятия возникла, когда я встретился с выпускником Cal Poly Стенли на конференции самоделкиных OpenSause, и он поведал мне то, что я уже знал из собеседований американских студентов: они изучают в вузе карты Карно, доходят до конечного автомата светофора, отдельно постигают классический 5-стадийный конвейер MIPS (ныне RISC-V), а потом идут на собеседование на работу, и - хоба! - выясняется что их карты Карно никого в индустрии не интересуют, а вопросы идут про сопряжение конвейера обработки данных (не процессорного!) и FIFO, чего они не проходили.

Привожу ниже мой отчет на английском.

A push for better workforce development in EE starts with the Verilog Meetup at Cal Poly San Luis Obispo

The idea to make a Verilog Meetup event at California Polytechnic State University, San Luis Obispo, started as a discussion between Yuri Panchul, a chip designer, and Stanley To, a CalPoly EE graduate working as an airspace contractor. This happened during an OpenSauce exhibition in the San Francisco Bay Area back in the summer. The discussion was joined by several student activists and the topic was the following:

It is not a secret to anybody in the digital chip design industry that students in many schools are not trained in solving microarchitectural problems with pipelines, FIFOs, credit-based flow control, arbiters etc, which constitute the bulk of work in front-end RTL design in the industrial projects: GPU, networking chips etc.

In a school, students usually have a Verilog class with FPGA labs that goes from gates to FSMs, plus a computer architecture class that presents the only kind of pipeline they know: a traditional 5-stage static pipeline for RISC-V (and MIPS in the past). This is not enough to work productively or even to pass a job interview, because many companies ask candidates questions on data pipelining.

So we decided to make an event to start the process of repairing the education system to better align it with industrial needs. To make the event more complete, we added a lecture on static timing analysis to microarchitecture, since designing a perfect pipeline should go along with measuring how many picoseconds are left in each stage we are building, and balancing the pipeline latency versus the maximum clock frequency.

Since learning digital design without doing is similar to learning to play a flute by watching slides on how to press the flute keys, we added FPGA boards and a path to move the design to a manufactured ASIC to our event.

We also covered Built-In Self-Test (BIST), memory repair with BIRA and BISR, a bit of emulation, and a talk on challenging AI. We tried to make FPGA exercises more fun by generating graphics on LCD screens. Then we also planned work work with music, but ran out of time.

Videos of the presentations:

Part 1/5. Yuri Panchul, a GPU chip designer, presents three open-source projects:

• Basics-Graphics-Music (BGM) – a set of SystemVerilog lab examples that used unchanged on 46 FPGA boards from the major vendors: Xilinx, Altera, Gowin and Lattice. The methodology allows isolating a student from the specifics of a board and a toolchain and concentrating on the things that matter: SystemVerilog language, RTL design methodology, static timing analysis (STA) and microarchitecture. This is accomplished by using scripts, wrappers and parameterization.

• SystemVerilog-Homework – a collection of SystemVerilog exercises from the beginning to the microarchitectural job interview level.

• A Verilog Meetup variant of the Tiny Tapeout Verilog Project Template, which allows seamless port of Verilog designs from the Basics-Graphics-Music (BGM) FPGA infrastructure to the Tiny Tapeout infrastructure that facilitates ASIC synthesis for the MPW shuttle manufacturing service using the Skywater foundry.

Part 2/5. This video has three sections:

1. Yuri Panchul, a GPU chip designer, continues to present the topics from Part 1/5.

2. Francisco Wilken, a Cal Poly lecturer who moved into the Silicon Valley industry, presents an overview of the ASIC RTL-to-GDSII flow.

3. Henry Evans, another Cal Poly graduate working as a design engineer in Silicon Valley, presents an overview of the Static Timing Analysis (STA).

Part 3/5. Two presentations:

• Henry Evans – Constrains 101.

• Francisco Wilken – BIST, BIRA, BISR: Build-In Self Test and Memory repair.

Part 4/5. Yuri Panchul explains the details of the Basics-Graphics-Music (BGM) infrastructure.

Part 5/5. Alex Huang, a University of California Santa Barbara student, teaches the basics of FIFO and presents two microarchitectural challenges for AI that can be used to also challenge the students:

• SystemVerilog Microarchitecture Challenge for AI No.1

• SystemVerilog Microarchitecture Challenge for AI No.2. Adding the Flow Control.

As a follow-up we discuss three projects:

• Making mockup interviews for the students over Zoom.

• Adding support for the Microchip FPGA toolchain in the BGM infrastructure. Ryan Cramer, the President of the Computer Architecture Research Project at Cal Poly, volunteered to do this.

• Adding support for some high-end Gowin boards, including a new inexpensive board with 138K LUTs and HDMI. This board is positioned as a game console, but can be repurposed for the student project to synthesize Linux-capable CPU cores and even multicore clusters.

Generally, Cal Poly is a long-time Xilinx user, however Xilinx Vivado became a 100GB monster with way too slow synthesis, plus Basys-3 boards are dated, so Xilinx-using schools explore the alternatives. Microchip/Microsemi/Actel is one of them, but Gowin might be even better because of its synthesis speed and high value-for-money ratio.

We also would like to thank everybody else contributing to the event, including:

• From Cal Poly: Pavan Bellam, Jack Karpinski, Eugene Petrov and Wilson Yu.

• From Verilog Meetup: Ramprakash Baskar, Dan Barrowman, Jorge Zavala.

• Jasmin from chili-chips.com.

• Victoria Grigoryev, a Cal Poly student who identified a bug in the current BGM infrastructure for the latest version of Gowin EDA for Apple Mac. I had an afterthought that maybe Victoria could fix this bug by herself as a student project, since this is a good exercise in Bash scripting, Apple specifics and EDA toolchain integration.