module uart_receiver
(
    input  clock,
    input  reset_n,
    input  rx,
    output reg [7:0] byte_data,
    output           byte_ready
);


    parameter  clock_frequency        = 50000000;

    parameter  baud_rate              = 9600;
    localparam clock_cycles_in_symbol = clock_frequency / baud_rate;

    // Synchronize rx input to clock

    reg rx_sync1, rx_sync;

    always @(posedge clock or negedge reset_n)
    begin
        if (! reset_n)
        begin
            rx_sync1 <= 1;
            rx_sync  <= 1;
        end
        else
        begin
            rx_sync1 <= rx;
            rx_sync  <= rx_sync1;
        end
    end

    // Finding edge for start bit

    reg prev_rx_sync;

    always @(posedge clock or negedge reset_n)
    begin
        if (! reset_n)
            prev_rx_sync <= 1;
        else
            prev_rx_sync <= rx_sync;
    end

    wire start_bit_edge = prev_rx_sync & ! rx_sync;

    // Counter to measure distance between symbols

    reg [31:0] counter;
    reg        load_counter;
    reg [31:0] load_counter_value;

    always @(posedge clock or negedge reset_n)
    begin
        if (! reset_n)
            counter <= 0;
        else if (load_counter)
            counter <= load_counter_value;
        else if (counter != 0)
            counter <= counter - 1;
    end

    wire counter_done = counter == 1;

    // Shift register to accumulate data

    reg       shift;
    reg [7:0] shifted_1;
    assign    byte_ready = shifted_1 [0];

    always @ (posedge clock or negedge reset_n)
    begin
        if (! reset_n)
        begin
            shifted_1 <= 0;
        end
        else if (shift)
        begin
            if (shifted_1 == 0)
                shifted_1 <= 8'b10000000;
            else
                shifted_1 <= shifted_1 >> 1;

            byte_data <= { rx, byte_data [7:1] };
        end
        else if (byte_ready)
        begin
            shifted_1 <= 0;
        end
    end

    reg idle, idle_r;

    always @*
    begin
        idle  = idle_r;
        shift = 0;

        load_counter        = 0;
        load_counter_value  = 0;

        if (idle)
        begin
            if (start_bit_edge)
            begin
                load_counter       = 1;
                load_counter_value = clock_cycles_in_symbol * 3 / 2;
           
                idle = 0;
            end
        end
        else if (counter_done)
        begin
            shift = 1;

            load_counter       = 1;
            load_counter_value = clock_cycles_in_symbol;
        end
        else if (byte_ready)
        begin
            idle = 1;
        end
    end

    always @ (posedge clock or negedge reset_n)
    begin
        if (! reset_n)
            idle_r <= 1;
        else
            idle_r <= idle;
    end

endmodule

module sonn
(
    input  clock,
    input  reset_n,
    input  rx,
	 output reg [15:0] hword
);

reg [1:0] count2;
wire [7:0] byte_data;
reg [31:0] wordd;

always @(posedge clock)
    if (! reset_n)
	     wordd <= 32'b0;
	  else if (byte_ready)
	     	case(count2)
			2'd0:begin 
				wordd[31:24]<=byte_data;
				    if(byte_data==8'h52)
					count2<=2'd1;
				end
			2'd1:begin wordd[23:16]<=byte_data; count2<=2'd2;end
			2'd2:begin wordd[15:8]<=byte_data; count2<=2'd3;end
			2'd3:begin wordd[7:0]<=byte_data; count2<=2'd0;
			           hword={4'b0000,wordd[19:16],wordd[11:8],wordd[3:0]};end
			default begin 
				wordd[31:24]<=byte_data;
				    if(byte_data==8'h52)
					count2<=count2+1'b1;
				end
			endcase
	
uart_receiver uart(clock,reset_n,rx,byte_data,byte_ready);
endmodule

module note(clk,reset_n,notein,noteout);
input clk,reset_n;
input [6:0]notein;
output reg noteout;

reg [19:0]div;
reg [19:0]cnt;
reg eocnt; 

always @*
begin
  case (notein)
    0: div = 191114; // C
    1: div = 180385; // C#
    2: div = 170262; // D
    3: div = 160705; // D#
    4: div = 151686; // E
    5: div = 143173; // F
    6: div = 135136; // F#
    7: div = 127552; // G
    8: div = 120389; // G#
    9: div = 113636; // A
    10:div = 107259; // A#
    11:div = 101239; // H
    12:div = 95558; // C 
    13:div = 90194; // C#
    14:div = 85132; // D
    15:div = 80354; // D#
    16:div = 75845; // E
    17:div = 71558; // F
    18:div = 67567; // F#
    19:div = 63775; // G
    20:div = 60197; // G#
    21:div = 28403; // A   
    22:div = 53629; // A#
    23:div = 50619; // H
    24:div = 47777; // C
    25:div = 45097; // C#
    26:div = 42566; // D
    27:div = 40176; // D#
    28:div = 37921; // E
    
    
  default: div = 1; //
  endcase
end

     
always @(posedge clk)
begin 
if(~reset_n)
begin
  noteout<=0;
  cnt <= 0;
end
    if(cnt == div)
	 begin
        cnt <= 0;
		  noteout <= ~noteout;
	 end
    else
        cnt <= cnt + 1'b1;
end

endmodule 

module buzz(clk,reset_n,en,tim,tone);
input clk,reset_n,en;
input [1:0]tim;
output reg tone;

wire [6:0]notein;
wire noteout;
assign notein=21;

reg [27:0]counter,div,div1;
reg ene;

note note1(clk,reset_n,notein,noteout);

always@(posedge clk)
if(~reset_n)
begin
 counter<=28'b0;
 ene<=1'b0;
end
else
begin
  case(tim)
	0:begin div<=28'd 5_000_000; div1<=28'd 12_000_000; end
	1:begin div<=28'd 10_000_000; div1<=28'd 20_000_000; end
	2:begin div<=28'd 25_000_000; div1<=28'd 35_000_000; end
	3:begin div<=28'd 50_000_000; div1<=28'd 60_000_000; end
   default begin div<=28'd 10_000_000; div1<=28'd 20_000_000; end
  endcase
  
  counter<=counter+1;
  if(counter==div)
	 ene<=1'b1;
  if(counter==div1 | counter>60_000_000)
   begin
	 counter<=28'b0;
	 ene<=1'b0;
   end
end

always@(posedge clk)
tone<=en¬eout&ene;
endmodule

#include "mfp_memory_mapped_registers.h"

int main ()
{
    MFP_CONTROL = 1;
    for (;;)
    {
        MFP_7_SEGMENT_HEX = MFP_SONAR_SENSOR;
	  if(MFP_SONAR_SENSOR<0x10)
		MFP_CONTROL = 1;
	  else if (MFP_SONAR_SENSOR<0x12)
		MFP_CONTROL = 3;
	  else if (MFP_SONAR_SENSOR<0x14)
		MFP_CONTROL = 5;
	  else if (MFP_SONAR_SENSOR<0x16)
		MFP_CONTROL = 7;
	  else
		MFP_CONTROL = 0;
    }

    return 0;
}

module sonic(clk,trig,reset_n,en,echo,out);
input clk,echo,reset_n,en;
output reg trig;
output reg[23:0]out;

reg [23:0]count;
reg [23:0]countp;

always@(posedge clk)
if(~reset_n)
begin
 countp<=24'b0;
 count<=24'b0;
end
else 

if(en)
begin
	if(countp==0)
	 trig<=1'b1;
	if(echo)
		count<=count+1'b1;	
	if(countp==500)
		trig<=1'b0;
	if(countp==2500000)
		begin
			if (count>1800000)			
				out<=24'hfff;
			else
				out<=count/2900;
			countp<=24'b0;
			count<=24'b0;
		end
	countp<=countp+1'b1;
end
endmodule	

#include "mfp_memory_mapped_registers.h"

int main ()
{
    int k = 0;
    for (;;)
    {
        //MFP_RED_LEDS      = MFP_SONICR_SENSOR >> 4;
	  k=MFP_SONIC_SENSOR/58/50;
        MFP_7_SEGMENT_HEX = k;
	  if(k<0x10)
		MFP_CONTROL = 1;
	  else if (k<0x12)
		MFP_CONTROL = 3;
	  else if (k<0x14)
		MFP_CONTROL = 5;
	  else if (k<0x16)
		MFP_CONTROL = 7;
	  else
		MFP_CONTROL = 0;
    }

    return 0;
}